It is “the same” for NVidia, ‘write your code
and run it’; it won’t be fast but it will run.

To “fix” it you go in and split up the loops into
threads and work to avoid data transfers…

One Video Card (from ATI or NVidia) offers
about a TeraFLOP or computing power, of which
you can _expect_ 10% and may sometimes get
30% of that. An extra 300 GFLOPs of additional
power for your 200 to 300 MFLOPs computer.

Some motherboards are designed to accept FOUR
Video Cards (and the Cards are also designed
to allow pairing and quading) so a “home-user”
can “easily” have a TeraFLOP on their Desk
for under $4000.

The GPU (or “a Video Card”) is on every (new)
Desktop Computer ready to lend it’s power to
specially compiled programs available today.

The “Cell/B.E.” or FPGA are not as good an
investment for most people since they are
not required (like a Video Card).

Your powerful Video Card can be used for
it’s intended (displaying output FAST on
your monitor) when it is not being used
for computation.

Your Sony PS3 (when not used for computation)
can double as a Video Game. What one would
do with a FPGA when it is not used for it’s
intended purpose it anyone’s guess.

If the Cell were cheaper in quantity and
available on a PCI Card it would be much
better, but that is not to be.

The FPGA is likely to be the fastest solution
but not the cheapest. Ultimatley it will
be the GPU (or 4 of them) that win this race.

>> In an earlier blog post, I have analyzed
>> that advantages of the Cell BE over other
>> acceleration technologies, like GPU and FPGA. ZZ

The GPU and FPGA (if on a PCI Card) can obtain
their input Data and transfer the calculation
result to the Host Computer faster than you
can send it over a Network from your Sony PS3.

Cam

On other fairly important point I think ought to be made here is around the ability to rely on the computed answers - what’s the use of all that speed if you can trust it, or have to run several iterations to build confidence?

That is to say, of the technologies (CPU, GPU, FPGA, and Cell/B.E.) only the CPU’s and Cell/B.E. have protection against Soft Errors (which are undetected corrupted data caused by things like cosmic rays). It’s a difference in a server heritage vs a consumer low cost target. Words like ECC, Parity, and CRC don’t appear in GPU’s (or typically FPGA’s - certainly they could be coded into FPGA’s, but at the cost of gates and effort etc).”

What a load of FUD. Firstly the cosmic rays issue, GPU’s use a similar plastic ball grid array packaging to CPU’s. In fact I’ve yet to see a GPU that doesn’t completely enclose the silicon in a cavity, unlike say the P3 FBGA. FPGA’s? They come in a variety of package options, also plastic, some for commercial applications, some for industrial, and some that are military radiation hardened. While traditional general purpose CPU’s can come in rad-hard packaging, however they’re typically surface mounted and are ~5x the cost of the commercial (for you Mike, the ones you buy at BestBuy when you’ve saved up lawn mowing money)

Accuracy? While none of the GPU vendors are exact to the IEEE standard with their rounding schemes, however its known that x86 isn’t 100% spot on in all cases. There are methods to correct this precision with respect to floating point unit size, in fact it was invented by Newton a few hundred years before electricity. With regards to FPGA’s, well the precision is your choice or left up to your choice of floating point core. There are dozens of companies that make off the shelf IP (Intellectual Property) cores that are IEEE compliant.

ECC? Typically you don’t see this in on chip memories, or at least that I’ve ever seen in 12 years of hardware development. As far as off chip memories, depends on what component. You can buy non-ECC or ECC memories, the choice is usually made in the Project Requirements phase of any development project. Do GPU’s use ECC? I’m sure vendors have and do, nVidia’s chips support ECC (at least to my knowledge the GeForce 6, the last datasheet of which I’ve seen). FPGAs? Of course.

Parity? GPU’s? No, it would almost be stupid to waste IO pins on the overhead given the project constraints. Maybe some vendors do, I’ve never seen it. FPGAs? Definately on every blockram or distributed ram I’ve ever generated on a Xilinx Spartan or Virtex FPGA. At a cost of gates? No, at a cost of one bit of parity per eight bits of data.

CRC? Why would one implement this in hardware other than for acceleration? Its a bit heavy weight for routine hardware to hardware tests. However it can easily be implemented on a GPU (why one would, I don’t know) and as with most of the BS you’ve spewed, there are probably a dozen vendors that sell IP cores that do this.

The only real difference between GPU’s and CPU’s is that GPU’s are logic dense with small amounts of on chip memory (typically a ratio of 70%-90% logic and 30%-10% on memory), while almost 60% of modern x86 cpu’s is on chip memory (L1, on die L2 cache, register file). With FPGA’s, it depends on the package selected, but they typically maintain a 90% logic to 10% memory ratio, at least with Xilinx’s line. As a result of this bias towards logic vs on chip memory and simple yet high speed architecture, they can be applied to a variety of engineering solutions and be coupled with a wide range of peripheral components.

-Burned